1. Field of the Invention
This invention relates generally to programmable logic devices (PLDs), and particularly to complex PLDs that may be reconfigured dynamically.
2. Field of Related Art
Programmable logic devices (PLDs) are well-known integrated circuits that may be programmed to perform logic functions. Numerous types of memory elements may be used in PLD architectures to provide programmability. One such memory cell, known as a flash memory cell, is both electrically erasable and programmable. A basic flash memory cell 100 is shown in FIG. 1a.
Flash memory cell 100 includes an access transistor 110 and a double-polysilicon storage transistor 120. Storage transistor 120 has a floating polysilicon gate 122 that is isolated in silicon dioxide and capacitively coupled to a polysilicon control gate 124. Storage transistor 120 also has a region of silicon dioxide between the floating gate 122 and a source 128 that is thin enough to permit electrons to tunnel to and from floating gate 122 when the proper bias voltages are applied to the terminals of storage transistor 120. The region of silicon dioxide is conventionally known as the "tunnel oxide."
Referring to FIG. 1a, storage transistor 120 is programmed by grounding its source 128, applying approximately five to 6 volts to its drain 126, and connecting its control gate 124 to a programming voltage V.sub.PP that is high relative to the operating voltage V.sub.CC. Typical values of the programming voltage V.sub.PP and operating voltage V.sub.CC are ten volts and five volts, respectively. With storage transistor 120 thus biased, electrons travel through the tunnel oxide to the floating gate 122, leaving the floating gate 122 with a net negative charge. This net negative charge shifts the threshold voltage V.sub.t (i.e., the voltage at which an MOS transistor begins to conduct) of storage transistor 120 in the positive direction to a voltage that is greater than V.sub.CC.
As shown in FIG. 1b, storage transistor 120 is erased by grounding control gate 124 and applying a relatively high voltage (e.g., eleven volts) to the source 128. This bias allows electrons to tunnel away from the floating gate 122 through the tunnel oxide to be swept away by the large positive voltage on the source 128. The loss of electrons (i.e., the loss of negative charge) on floating gate 122 shifts the threshold voltage V.sub.t of storage transistor 120 in the negative direction to a voltage that is less than V.sub.CC.
When erasing storage transistor 120, it is possible to remove too many electrons from floating gate 122, resulting in excess positive charge on floating gate 122. This condition is commonly known as "over-erase." Access transistor 110 is provided to prevent storage transistor 120 conducting in the event that storage transistor 120 is over-erased.
When the PLD operates as a logic device, each of the storage transistors (e.g., storage transistor 120) has V.sub.CC applied to its control gate 124. The state of each storage transistor may then be "read" by determining whether the storage transistor conducts. If the storage transistor is programmed, V.sub.CC is less than the threshold voltage V.sub.t so the storage transistor will not conduct if, on the other hand, the storage transistor is erased, V.sub.CC will be sufficient to turn the storage transistor on.
After flash memory cell 100 is programmed or erased, a test is generally performed to verify the state of storage transistor 120. For example, to verify that storage transistor 120 is properly programmed, a verify-program voltage V.sub.VP is applied to the control gate 124 to determine whether the threshold voltage V.sub.t of storage transistor 120 is sufficiently high to keep storage transistor 120 from conducting when V.sub.CC is applied to the control gate 124. The verify-program voltage V.sub.VP applied to the control gate 124 is greater than V.sub.CC by a safety factor of, for example, 3 volts. This safety factor allows for noise and for a possible negative shift of the threshold voltage V.sub.t caused by electrons escaping from the floating gate 122 over the life of memory cell 100.
As shown in FIG. 1c, when the programmed or erased state of storage transistor 120 is verified, V.sub.CC is applied to the control gate of access transistor 110 to turn access transistor 110 on. A sense amplifier 150, coupled across the series connected access transistor 110 and storage transistor 120, determines whether storage transistor 120 conducts. If the threshold voltage V.sub.t of storage transistor 120 is sufficiently high, over eight volts for example, a verify-program voltage V.sub.VP of eight volts will not turn storage transistor 120 on. As a result, verify sense amplifier 150 will not sense current through the series coupled transistors 110 and 120.
After storage transistor 120 is erased, the state of erasure may be verified by ensuring that storage transistor 120 conducts with a low V.sub.T threshold margin applied to control gate 124. This erase threshold margin value is about 2 V. V.sub.CC is then applied to the control gate of access transistor 110 to allow sense amplifier 150 to access storage transistor 120. If storage transistor 120 is properly erased, verify sense amplifier 150 will detect a current through series transistors 110 and 120 with the two-volt verify-erase voltage V.sub.VE applied to the control gate 124 and V.sub.CC applied to the control gate of access transistor 110.
When a flash PLD functions as a logic device (i.e., when the PLD is in the "logic mode"), the PLD requires only a five-volt power supply. However, as discussed above, other modes, such as program and erase, require additional power supply voltages greater than V.sub.CC. To satisfy the requirement of additional power supply voltages, conventional PLDs use an external power supply capable of providing at least a programming voltage on a terminal V.sub.PP.
FIG. 2 shows a typical program/verify scheme for a conventional storage transistor of a PLD. The following discussion describes this program/verify scheme as applied to storage transistor 120.
The program/verify signal PGMVFY is an internally-provided logic signal. When PGMFVY goes from zero to five volts (i.e., from a logic zero to a logic one) the PLD enters the. program/verify mode. In the program-verify mode, V.sub.PP begins at approximately twelve volts to program selected storage transistors, in this case storage transistor 120. An externally generated program-enable signal PGM.sub.EN (active-low) goes to zero volts while V.sub.PP is held at twelve volts. The low PGM.sub.EN signal activates various components (not shown) in the PLD to provide the appropriate programming bias voltages to storage transistor 120. PGM.sub.EN remains zero for a time TP long enough to program storage transistor 120.
After storage transistor 120 has been programmed as described above, the PGM.sub.EN signal returns to five volts and the externally supplied programming voltage from terminal V.sub.PP is brought to eight volts for the verify cycle. Once the signal on terminal V.sub.PP settles at eight volts, an externally provided verify-enable signal VFY.sub.EN (active-low) is brought from five to zero volts, thereby enabling the verify cycle.
During the verify cycle, when the verify enable signal is low the eight-volt verify signal on terminal V.sub.PP is applied to the control gate of storage transistor 120 to determine whether the threshold voltage V.sub.t of storage transistor 120 is sufficiently high to keep storage transistor 120 from conducting with eight volts applied to control gate 124.
The transition time T.sub.TR for the programming voltage on terminal V.sub.PP to drop from twelve to eight volts is typically several microseconds. By itself, transition time T.sub.TR is relatively short. However, there are generally tens of thousands of storage transistors to be programmed on a complex PLD. The cumulative effect of these transition times T.sub.TR is undesirable delay, especially when the testing process is automated. Hence, there exists a need for a complex PLD that may be tested more quickly than conventional complex PLDs.
A second problem that exists in PLDs is that the level of voltage that must be applied to the gate of a storage transistor (e.g., storage transistor 120) to cause the storage transistor to conduct enough current to trip the associated sense amplifier (e.g., verify sense amplifier 150) may vary due to process variations that effect the threshold voltage V.sub.t of the storage transistor and the sensitivity of the associated sense amplifier. Therefore, manufacturers experiment to determine the appropriate verify-program and verify-erase voltages. For example, experimentation may indicate that the verify-program voltage V.sub.VP should be 7.8 volts instead of 8 volts, in which case it would be necessary to adjust the verify-program V.sub.VP voltage to 7.8 volts.
Manufacturers of conventional PLDs must determine the actual values of the verify-program voltage V.sub.VP and the verify-erase voltage V.sub.VE and provide these values to the user (e.g. a third-party programmer). The user must then tailor the testing input voltages accordingly. Unfortunately, the need for such tailored voltages complicates the task of verifying the programmed and erased stages of storage transistors in PLDs and requires the user provide an adjustable power supply.
A third problem relates to the fact that each prior art device requires that programming and verify voltages be supplied by one or more external power supplies. This has become especially problematic for PLDs that are in-system programmable (i.e., PLDs that may be reconfigured without removing the PLD from the system in which it acts as a logic device). The need to supply programming voltages that are not necessary in the logic mode requires that the system employing the PLD include at least one additional power supply and that the PLD include at least one additional input pin. Moreover, as discussed above, the supply voltages used must be tailored to the particular needs of particular PLDs, depending on the required verify voltages. Hence, there exists a need for a PLD that does not require the use of external power supply voltages and that relieves the user of having to adjust power supply voltages to account for variations in verify voltage requirements.